Memory controllers use both a command bus and a data bus for communicating with a memory device. The command bus is used to send address information as well as command instructions for operations such as read, write, activate, and precharge (activate and precharge may also be more commonly known as row/page open or close, respectively). Meanwhile, the data bus is used to transfer read and write data to and from the memory device. Such a memory device and memory controller combination is illustrated in the computer system 100 of FIG. 1. As illustrated in FIG. 1, an exemplary computer system 100 may comprise a Northbridge 102, which is traditionally part of a logic chipset on a motherboard. The Northbridge 102 can either be a separate chip or part of another chip, such as a CPU. The Northbridge 102 may be interconnected with an exemplary graphics interface 104, a CPU 106, and a volatile memory (RAM) 108. In one exemplary embodiment, the memory device 108 can be a dynamic random-access memory (DRAM) that is interconnected to the Northbridge 102 by a memory controller 110. As further illustrated in FIG. 1, the memory controller 110 may be interconnected to the memory device 108 by a command bus 112 and a data bus 114. As further illustrated in FIG. 1, the Northbridge 102 can also be interconnected with a Southbridge 116 that serves to interconnect with other well-known computer interfaces, such as a PCI local bus, USB, ISA buses, IDE interfaces, and etc.
As illustrated in FIGS. 2A, 2B, and 2C, each command operation issued by the memory controller 110, via the command bus 112, such as a read command, results in a fixed number of data transfers from the memory device 108 to the memory controller 110 via the data bus 114. This fixed number is referred to as the minimum burst length. For example, sDDR2 memory uses a burst length of 4, sDDR3 uses a burst length of 8, and mobile Wide-IO uses a burst length of 2 or 4.
FIG. 2A illustrates a burst length of 1:1, FIG. 2B illustrates a burst length of 2:1, and FIG. 2C illustrates a burst length of 4:1. As illustrated in FIGS. 2A-2C, the burst length defines a command to data bandwidth ratio, where a burst length of 1 means that for every command using a clock cycle of an exemplary 1 ns, the returned data will also use an exemplary 1 ns of time. Therefore, as illustrated in FIG. 2B, a burst length of 2 means that a transmitted command using a clock cycle of 1 ns will see returned data using an exemplary 2 ns of time. Lastly, as illustrated in FIG. 2C, a burst length of 4 means that for every command using a clock cycle of 1 ns, the returned data will use an exemplary 4 ns of time. Or put another way, with a 2:1 ratio, for every clock cycle a command is given, two clock cycles of data are returned, while with a 4:1 ratio, for every clock cycle a command is given, four clock cycles of data are returned.
A typical memory controller 110 sends multiple commands usually greater than one for each data transfer on the bus. This number can go higher than 2 for some multi-rank, closed-page implementations of a memory controller 110. If a number of commands needed to communicate with the memory device 108 becomes larger than the minimum burst length, the effective utilization of the memory interface reduces proportionally. For example, if the command-to-minimum-burst-length ratio is 2:1, as illustrated in FIG. 2B, then every other slot on the data bus will be unutilized, reducing the effective data bandwidth by 50%. As illustrated in FIGS. 2B and 2C, when a read command is issued, the data sent back to the memory controller 110 is dependent upon the minimum burst length. In FIG. 2B, when a read command RD0 is received, the memory device 108 returns not only the requested data at the RD0 address, but also an additional data at an address equal to the RD0 address plus some fixed predefined address offset x (RD0+x). In FIG. 2C, when a read command RD0 is received, the memory device 108 returns not only the requested data at the RD0 address, but also three additional data at addresses equal to the RD0 address plus some fixed predefined address offset x (RD0+x, RD0+2x, and RD0+3x).
In other words, while burst lengths of 2 and 4, or higher, provide additional command bandwidth such that maintenance commands (e.g., pre-charge commands, activate commands, and other commands like refresh and calibration) can be sent while the previous read/write command is being executed without disrupting the data stream, the wide burst length requirements result unfortunately in data inefficiencies as the extra data returned (RD0+x) may not be needed and will be discarded in the memory controller 110.
With the advent of Wide-IO memories with wide 128/256 bit data interfaces, this problem is becoming more severe. To keep the minimum prefetch in check, these devices use small burst lengths of only one or two. However, with current command mapping and a burst length of 1, it is not possible to get a data bus bandwidth utilization comparable to current devices with larger burst lengths. When maintenance commands are sent, a read or write data command cannot be sent and there will be a break in the data stream. As will be discussed herein, such breaks in the data stream due to the necessity of performing maintenance operations can result in up to a 25% loss in data bus bandwidth efficiency for small burst length devices. While higher data bus bandwidth utilization can be achieved by increasing the width of the command interface to allow more commands to be issued, such increases come at the cost of significantly increased pin counts.